1. Field of the Invention
The invention relates to a silicon semiconductor component, with a wafer-like silicon semiconductor body with an edge contour made by an etching technique, which has a p-region parallel to a principal surface of the semiconductor body and has in this principal surface a passivating ditch, into which leads a pn-junction extending between the more heavily doped p-region and a less havily doped n-region, in which the edge contour has in the vicinity of a flank length, between the emergence of the pn-junction into the passivating ditch and this principal surface of the semiconductor body, a small angle of inclination of 1.degree. to 7.degree..
2. Description of the Prior Art
Silicon semiconductor components are customarily produced by simultaneously producing several semiconductor components on a silicon wafer and separating them later, for instance by scribing, sawing or by means of a laser beam. A component edge is produced by the separation at which pn-junction barrier surfaces come to the surface and thereby come into contact with the atmosphere surrounding the component. The shape of the edge has considerable influence on the blocking voltage of the components that can be attained. The attempt is to bevel the edge of the component in such a way that an angle between the pn-junction surface and the component surface as flat as possible results, because thereby, lower and better manageable electric field strength are obtained at the surface. Such a desirable bevel of the edge can be obtained by etching a ditch.
For manufacturing components in Mesa technology, ditches are etched along the edges of the individual components on the silicon wafer. The ditches must be deep enough to separate the blocking pn-barrier junctions which are usually located at a depth of 60 to 80 .mu.m. After the etching, the ditches are filled with a suitable passivating glass, so that the pn-junctions are covered up and are protected against influences of the environment.
Passivating ditches which are etched into the wafer along separation lines of the individual components are very popular.
The ditches are separated along their center line for dividing the wafer into individual components. Thereby, individual components are produced as shown by way of an example in FIG. 1. FIG. 1 shows a known silicon semiconductor component 1 in Mesa technology with its p and n-layers, a metallization 2 on the surfaces and with passivating glass 3 in the edge zone.
A disadvantage of this form of ditches is that cracks can occur in the passivating glass during the separation of the silicon wafer, for instance due to mechanical stresses, whereby the attainable blocking voltage is reduced.
Another known form of the passivating ditch is the so-called moat, which is shown in FIG. 2. In the moat, the active part of the silicon component 1 is separated from the not used edge portion or from an adjacent component by a separate ditch G which is filled with passivating glass 3. On a silicon wafer with several components which are to be separated later, ditches are made to the left and right of the separation lines provided and filled with glass. In separating the wafer into individual components, only silicon but no passivating glass is therefore separated. A disadvantage of the moat with the known edge contour is that as a rule, narrow ditches with steep flanks are made for reasons of space, which results in increased field strength which can lead to considerably reduced blocking voltages. In addition, it is difficult with ditches up to 100 .mu.m deep, because of the large level difference, to cover the edges with passivating glass without defect.
German Published Non-Prosecuted Application (DE-OS) No. 28 51 375 discloses a design of the ditch for the manufacture of semiconductor components in Mesa technology which is suitable for components with a blocking voltage of up to about 1000 V. The ditch is made in two steps. For this purpose, a narrow deep ditch is etched first and subsequently, the ditch is widened in an upper region in a second etching operation. The entire ditch is filled with a passivating glass. The purpose of this arrangement is to keep traces of a metallization which is applied in a later process step and which could penetrate between the glass passivating layer and the silicon surface, away from the pn-junction surface, since the pn-junction surface lies in the vicinity of the narrow and steep portion of the ditch which is made first, as explained on page 6 of the cited published non-prosecuted application. It is therefore improbable that the metallization material travels the long path under the glass in the flat part of the ditch through to the steep part of the ditch. However, this arrangement has the same disadvantages with respect to the inverse voltage strength which had been mentioned, for instance for the customary moat with a pn-junction in a steep part of the ditch.
In the paper "The Theory and Application of a Simple Etch Contour for Near Breakdown Voltage in Plane and Planar p-Junctions" by V. A. K. Temple and M. S. Adler in IEEE Transactions of Electron Devices, Vol. ED-23, No. 8, August 1976, Pages 950 to 955 and in the paper "Practical Aspects of the Depletion Etch Method in High-Voltage Devices" by V. A. K. Temple in IEEE Transactions on Electron Devices, Vol. ED-27, No. 5, May 1980, Pages 977 to 982, an edge contour is described in which the space charge zone is etched in the diffused layer substantially parallel to the pn-junction surface. Such an edge contour is suitable for high breakdown voltages. The attainable breakdown voltages almost correspond to the bulk breakdown voltages. However, the etching depth optimum therefore must be reached very accurately. A small deviation from the optimum depth leads to a drastic decline of the breakdown voltage. It will be apparent that such a procedure and such an edge contour are not suitable for mass production. The method is described in the cited publications only for the production of individual elements. It is not suitable for the practical case where several chips are to be etched together on a silicon wafer as is customary, for instance in the manufacture of glass-passivated components. It would be impossible to observe the required narrow etching tolerances.
French Patent Application (FR-OS) No. 24 68 207 describes a silicon semiconductor component with a wafer-shaped silicon semiconductor body with an edge contour made by etching techniques in which the edge contour has a a small angle of inclination of less than 10.degree. or less than 6.degree. in a passivating ditch and the principal surface of the semiconductor body having the passivating ditch between the emergence of a pn-junction extending between a more heavily doped p-area and a less heavily doped n-area. In this publication, a first conductance type (p or n) and a second conductance type (n or p) is mentioned which means that the conductivities can be interchanged. The same applies, of course, also to the present invention in which a selected sequence of the conductivities is assumed for ease of description. According to French Patent Application (FR-OS) No. 24 68 207, one cannot get along without mechanical processing steps (grinding, sand-blasting) for the preparation of the ditches. After the mechanical processing step which determines substantially the ditch contour, chemical overetching follows in order to remove mechanically damaged layers. The edge contour is no longer changed substantially here. The mechanical preparation of the edge contour, particularly of moat ditches, is very costly.